Senior RF Test Engineer

Locations

Campbell, California

About the Position:

As a Senior RF Test Engineer, you must be able to drive, develop and implement complete ATE HW and SW solution for Keyssa’s connectivity chips and systems. These responsibilities will involve development of ATE tests per specification, ATE to bench correlation, PVT characterization of product performance and release to production test programs.

Roles and Responsibilities:

  • Lead test development of high-speed digital and EHF radio designs from DFT concept to production.
  • Own ATE hardware design with out of box thinking to overcome EHF testing challenges.
  • Create advanced Test Methods with C/C++/Java in software development to achieve multisite testing flawlessly.
  • Manage test vector translation and debug, working with design team.
  • Able to work under pressure to quickly implement any coverage/quality issues.
  • Understand Failure analysis and package/die qualification flows.
  • Work with OSAT vendors to release/correlate test programs and address issues quickly if there is any.
  • Generate required documents to follow quality management process.

Qualifications Desired:

  • 5+ years’ experience in wireless CMOS RF or EHF 60GHz (like 802.11ad, WiGig, WirelessHD) and digital logic, mixed signal test engineering field.
  • Experience in test development with C/C++ /Java related to Automated Test Equipment (Advantest 93K/Smartscale, Teradyne Ultraflex) in semiconductor industry is required
  • Knowledge in antenna horn, 60GHz EM beam theory, EHF physics and theory.
  • Excellent SW/HW and troubleshooting, debugging and problem-solving skills
  • Hands-on experiences with RF test equipment, signal generators and analyzers, oscilloscope, etc.
  • Good presentation, written and verbal skills.
  • Ability to perform multi-tasks and good project management skills.
  • Willingness to travel and flexibility in working hours.
  • Strong data analysis and great attention to details.
  • Familiarity with design for test (DFT) techniques and structural tests such as Scan/ATPG, JTAG, and memory BIST is desirable

Educational Requirements:

  • BSEE required, MSEE preferred
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